Performance of digital adder architectures in 180nm CMOS standard-cell technology
| dc.contributor.author | Pilato, Luca | |
| dc.contributor.author | Saponara, Sergio | |
| dc.contributor.author | Fanucci, Luca | |
| dc.contributor.editor | Pinker, Jiří | |
| dc.date.accessioned | 2019-10-09T05:37:15Z | |
| dc.date.available | 2019-10-09T05:37:15Z | |
| dc.date.issued | 2016 | |
| dc.description.abstract-translated | In this paper, we present and compare the design and the performances of ten different implementations for a 16-bit adder in a 180nm CMOS standard-cell technology. Ripple carry adder, increment adder, triangle adder, uniform and progressive carry select adder, uniform and progressive carry bypass adder, conditional adder, ripple carry look ahead adder and hierarchical carry look ahead adder are taken into account. Every architecture is explained, highlighting the pros and cons. Finally, the results of area complexity, worst path timing and average power consumption for each implementation are shown. | en |
| dc.format | 4 s. | cs |
| dc.format.mimetype | application/pdf | |
| dc.identifier.citation | 2016 International Conference on Applied Electronics: Pilsen, 6th – 7th September 2016, Czech Republic, p.211-214. | en |
| dc.identifier.isbn | 978–80–261–0601–2 (Print) | |
| dc.identifier.isbn | 978–80–261–0602–9 (Online) | |
| dc.identifier.issn | 1803–7232 (Print) | |
| dc.identifier.issn | 1805–9597 (Online) | |
| dc.identifier.uri | http://hdl.handle.net/11025/35283 | |
| dc.language.iso | en | en |
| dc.publisher | Západočeská univerzita v Plzni | cs |
| dc.rights | © Západočeská univerzita v Plzni | cs |
| dc.rights.access | openAccess | en |
| dc.subject | sčítání | cs |
| dc.subject | zpoždění | cs |
| dc.subject | počítačová architektura | cs |
| dc.subject | poptávka po energii | cs |
| dc.subject | logická brána | cs |
| dc.subject | technologie CMOS | cs |
| dc.subject | teorie složitosti | cs |
| dc.subject.translated | adders | en |
| dc.subject.translated | delays | en |
| dc.subject.translated | computer architecture | en |
| dc.subject.translated | power demand | en |
| dc.subject.translated | logic gate | en |
| dc.subject.translated | CMOS technology | en |
| dc.subject.translated | complexity theory | en |
| dc.title | Performance of digital adder architectures in 180nm CMOS standard-cell technology | en |
| dc.type | konferenční příspěvek | cs |
| dc.type | conferenceObject | en |
| dc.type.status | Peer-reviewed | en |
| dc.type.version | publishedVersion | en |
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