Defying the Memory Bottleneck in Hardware Accelerated Collision Detection

Abstract

A novel approach for hardware-accelerated high-speed collision detection is presented in this article. It focuses on dedicated hardware for collision detection queries and its interaction with the memory interface. A specialised tree-traversal algorithm is presented that exploits arbitrary memory interfaces optimally to minimise delay of collision queries. Along with this a novel caching technique is introduced that combines high-speed access to the bounding-volume hierarchy with minimal resource consumption. Simulation and synthesis results are presented that prove the conjunction of both techniques to enable real-time collision queries at rates required by force-feedback while fitting onto a standard field-programmable gate array.