Reduction of divider circuit errors

dc.contributor.author	Pilśniak, Adam
dc.contributor.author	Holajn, Piotr
dc.date.accessioned	2014-07-29T12:25:25Z
dc.date.available	2014-07-29T12:25:25Z
dc.date.issued	2013
dc.description.abstract	The analog divider based on transconductance multiplier is analyzed to determine its uncertainty due to voltage offsets. In the paper is shown, the divider errors can be reduced.	en
dc.format	1 s.	cs
dc.format.mimetype	application/pdf
dc.identifier.citation	CPEE – AMTEE 2013: Joint conference Computational Problems of Electrical Engineering and Advanced Methods of the Theory of Electrical Engineering: 4th – 6th September 2013 Roztoky u Křivoklátu, Czech Republic, p. III-5.	en
dc.identifier.isbn	978-80-261-0247-2
dc.identifier.uri	http://hdl.handle.net/11025/11619
dc.language.iso	en	en
dc.publisher	University of West Bohemia	en
dc.relation.ispartofseries	CPEE – AMTEE 2013: Joint conference Computational Problems of Electrical Engineering and Advanced Methods of the Theory of Electrical Engineering	en
dc.rights	© University of West Bohemia	en
dc.rights.access	openAccess	en
dc.subject	transkonduktanční násobičky	cs
dc.subject	analogové děliče	cs
dc.subject	kompenzace chyb	cs
dc.subject.translated	transconductance multipliers	en
dc.subject.translated	analog dividers	en
dc.subject.translated	error compensation	en
dc.title	Reduction of divider circuit errors	en
dc.type	konferenční příspěvek	cs
dc.type	conferenceObject	en
dc.type.status	Peer-reviewed	en
dc.type.version	publishedVersion	en

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