Implementation of JESD204B Receiver for Interleaved Analog to Digital Convertor in FPGA

Abstract

With the continuously increasing frequency bands of signals in the world of electronics, new challenges in their processing constantly arise. This fact pushes both component manufacturers and their users to develop new methods to keep pace with these demands. One approach is to increase the conversion speed of traditional analog-to-digital converters (ADCs). Another possible solution is to use the time-interleaving technique, which employs an array of slower converters working in parallel. Modern ADCs, especially those operating in the range of units to tens of GSPS, feature the JESD204 communication standard, which transmits digitized data to the next system, typically an FPGA. Therefore, this system must implement a receiver for this standard, incorporating all necessary functionalities. We have designed and implemented a receiver for this standard for the FPGA circuit. Subsequently, the functionality and characteristics were verified on a real-time interleaved sampling system.