New structures of 2n ± 1 modular adders for FPGAs

dc.contributor.authorYounes, Dina
dc.contributor.authorŠteffan, Pavel
dc.contributor.editorPihera, Josef
dc.contributor.editorSteiner, František
dc.date.accessioned2012-11-12T08:57:25Z
dc.date.available2012-11-12T08:57:25Z
dc.date.issued2011
dc.description.abstract-translatedTwo new structures of residue number system (RNS) adders for moduli 2n –1, 2n +1 are presented in this paper. The main idea is the utilization of the prefix computation technique in order to make the correction stage enclosed in the addition process instead of leaving it as the last stage of the modular addition. This provides faster and more efficient applications. Both designs allow efficient implementation on field programmable gate array (FPGA). Carry ripple adders (CRA) were utilized in the two structures due to the dedicated carry ripple logic built-in FPGAs. The proposed designs were implemented on Spartan-3 xc3s200-ft256-4 FPGA. A comparison with already published designs was done in terms of time and area consumption and showed significant time savings up to 44.7%.en
dc.format4 s.cs
dc.format.mimetypeapplication/pdf
dc.identifier.citationElectroscope. 2011, č. 4, EDS 2011.cs
dc.identifier.issn1802-4564
dc.identifier.urihttp://147.228.94.30/images/PDF/Rocnik2011/Cislo4_2011/r5c4c8.pdf
dc.identifier.urihttp://hdl.handle.net/11025/627
dc.language.isoenen
dc.publisherZápadočeská univerzita v Plzni, Fakulta elektrotechnickács
dc.relation.ispartofseriesElectroscopecs
dc.rightsCopyright © 2007-2010 Electroscope. All Rights Reserved.en
dc.rights.accessopenAccessen
dc.subjectsoustava zbytkových třídcs
dc.subjectmodulo 2n+1 sčítačkycs
dc.subjectprogramovatelná hradelná polecs
dc.subject.translatedresidue number systemen
dc.subject.translatedmodulo 2n+1 addersen
dc.subject.translatedfield programmable gate arrayen
dc.titleNew structures of 2n ± 1 modular adders for FPGAsen
dc.typekonferenční příspěvekcs
dc.typeconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen

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