Implementace genetického algoritmu do obvodu FPGA

dc.contributor.author	Burian, Petr
dc.contributor.editor	Pihera, Josef
dc.contributor.editor	Steiner, František
dc.date.accessioned	2012-10-04T11:46:18Z
dc.date.available	2012-10-04T11:46:18Z
dc.date.issued	2008
dc.description.abstract-translated	This paper deals with the implementation of a standard genetic algorithm by an FPGA circuit. It examines the various features of this algorithm. The main goal of this work is building of an evolvable combinational circuit. Demands imposed on an FPGA circuit are researched as well.	en
dc.format	4 s.	cs
dc.format.mimetype	application/pdf
dc.identifier.citation	Electroscope. Elektrotechnika a informatika 2008, p. [13-16].	en
dc.identifier.isbn	978-80-7043-702-5
dc.identifier.issn	1802-4564
dc.identifier.uri	http://hdl.handle.net/11025/497
dc.language.iso	cs	cs
dc.publisher	Západočeská univerzita v Plzni, Fakulta elektrotechnická	cs
dc.relation.ispartofseries	Electroscope	cs
dc.rights	Copyright © 2007-2010 Electroscope. All Rights Reserved.	en
dc.rights.access	openAccess	en
dc.subject	standardní genetický algoritmus	cs
dc.subject	vyvíjející se obvody	cs
dc.subject.translated	standard genetic algorithm	en
dc.subject.translated	evolvable hardware	en
dc.title	Implementace genetického algoritmu do obvodu FPGA	cs
dc.type	konferenční příspěvek	cs
dc.type	conferenceObject	en
dc.type.status	Peer-reviewed	en
dc.type.version	publishedVersion	en

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