Timepix4 chipboard and readout concept

Abstract

This paper presents a modular readout and chipboard concept developed for the Timepix4 hybrid pixel detector, a high-performance ASIC featuring 448 x 512 pixels and sub-nanosecond timing resolution. Building on the success of Timepix3, Timepix4 supports both frame-based and data-driven acquisition modes with data rates up to 3.6 MHits/mm2/s and 195 ps time binning. The chip can be integrated via wire-bonding or Through-Silicon-Via (TSV) technology, allowing full four-side tiling for scalable detector arrays. The modular chipboard system, consisting of a detector module and a baseboard, simplifies power delivery and data transmission using a single 12 V supply and Ethernet-style cabling. A commercial FPGA-based readout supports up to four detectors with Gigabit Ethernet and PCIe interfaces. The concept was successfully validated at CERN SPS with heavy-ion beams, demonstrating system stability and high data integrity. Ongoing development focuses on enhanced power and cooling systems, multi-chip integration, and improved software support for advanced experimental setups.