Hardware-accelerated ray-triangle intersection testing for high-performance collision detection
Date issued
2007
Journal Title
Journal ISSN
Volume Title
Publisher
Václav Skala - UNION Agency
Abstract
We present a novel approach for hardware-accelerated collision detection. This paper describes the design of the hardware
architecture for primitive inference testing components implemented on a multi-FPGA Xilinx Virtex-II prototyping system.
This paper focuses on the acceleration of ray-triangle intersection operation which is the one of the most important operations
in various applications such as collision detection and ray tracing. Also, the proposed hardware architecture is general for
intersection operations of other object pairs such as sphere vs. sphere, oriented bounding box (OBB) vs. OBB, cylinder vs.
cylinder and so on.
The result is a hardware-accelerated ray-triangle intersection engine that is capable of out-performing a 2.8GHz Xeon processor,
running a well-known high performance software ray-triangle intersection algorithm, by up to a factor of seventy. In addition,
we demonstrate that the proposed approach could prove to be faster than current GPU-based algorithms as well as CPU based
algorithms for ray-triangle intersection.
Description
Subject(s)
detekce kolizí, grafický hardware, testování průsečíku, sledování paprsku
Citation
Journal of WSCG. 2007, vol. 15, no. 1-3, p. 17-24.