Area-Efficient Analog Operations by Dynamicly-Reconfigured Switched-Capacitor Circuits

dc.contributor.authorKobayashi, Fuminori
dc.contributor.authorHiguchi, Shintaro
dc.contributor.authorZain, Mohamad
dc.contributor.authorRamli, Azreen Bin
dc.contributor.editorPinker, Jiří
dc.date.accessioned2019-10-17T11:12:08Z
dc.date.available2019-10-17T11:12:08Z
dc.date.issued2018
dc.description.abstract-translatedTogether with software on a micro-controller, simple additional hardware can implement electronics with less cost and power. Though analog before digitization, in particular, is effective, it comes with a drawback of larger circuit area. This paper proposes a scheme to shrink area by devising clock waveforms of switched-capacitor devices, through dynamic circuit restructuring. Application to a D/A converter using weighted adder is presenteden
dc.format4 s.cs
dc.format.mimetypeapplication/pdf
dc.identifier.citation2018 International Conference on Applied Electronics: Pilsen, 11th – 12th September 2018, Czech Republic, 77-80.en
dc.identifier.isbn978–80–261–0721–7
dc.identifier.issn1803–7232
dc.identifier.urihttp://hdl.handle.net/11025/35475
dc.language.isoenen
dc.publisherZápadočeská univerzita v Plznics
dc.rights© Západočeská univerzita v Plznics
dc.rights.accessopenAccessen
dc.subjectCypress PSoCcs
dc.subjectnestejnoměrné časovánícs
dc.subject.translatedCypress PSoCen
dc.subject.translatednonuniform clockingen
dc.titleArea-Efficient Analog Operations by Dynamicly-Reconfigured Switched-Capacitor Circuitsen
dc.typekonferenční příspěvekcs
dc.typeconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen

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