Serial IIR filter structure generator for ASICs

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dc.contributor.authorPristach, Marián
dc.contributor.authorFujčík, Lukáš
dc.contributor.editorPihera, Josef
dc.contributor.editorSteiner, František
dc.date.accessioned2013-01-30T07:54:20Z
dc.date.available2013-01-30T07:54:20Z
dc.date.issued2012
dc.description.abstract-translatedThe paper presents generator of an infinite impulse response (IIR) digital filter structure for implementation in application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. The serial architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.en
dc.format4 s.cs
dc.format.mimetypeapplication/pdf
dc.identifier.citationElectroscope. 2012, č. 6, EDS 2012.cs
dc.identifier.issn1802-4564
dc.identifier.urihttp://hdl.handle.net/11025/1045
dc.language.isoenen
dc.publisherZápadočeská univerzita v Plzni, Fakulta elektrotechnickács
dc.relation.ispartofseriesElectroscopecs
dc.rights© 2012 Electroscope. All rights reserved.en
dc.rights.accessopenAccessen
dc.subjectdigitální filtry s nekonečnou impulzní odezvoucs
dc.subjectgenerátorycs
dc.subjectintegrované obvodycs
dc.subject.translatedinfinite impulse response digital filtersen
dc.subject.translatedgeneratorsen
dc.subject.translatedintegrated circuitsen
dc.titleSerial IIR filter structure generator for ASICsen
dc.typekonferenční příspěvekcs
dc.typeconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen

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Číslo 6 - EDS 2012 (2012)
Číslo 6 - EDS 2012 (2012)