Controller fixed-point optimization with genetic algorithms

dc.contributor.authorWolfram, Heiko
dc.date.accessioned2019-09-25T10:45:16Z
dc.date.available2019-09-25T10:45:16Z
dc.date.issued2015
dc.description.abstract-translatedThis work describes a way to optimize the controller fixed-point representation in programmable logic devices (eg. FPGA) with genetic algorithms. The optimization uses the error between floating-point and fixed-point representation as well as a quantization noise error model. Thus, both terms allow weighting between the to be expected theoretical and actually occurred simulation error. This task could be automated easily due to the script features of the simulation system.en
dc.format6 s.cs
dc.format.mimetypeapplication/pdf
dc.identifier.citation2015 International Conference on Applied Electronics: Pilsen, 8th – 9th September 2015, Czech Republic, p.279-284.en
dc.identifier.isbn978-80-261-0385-1 (Print)
dc.identifier.isbn978-80-261-0386-8 (Online)
dc.identifier.issn1803-7232 (Print)
dc.identifier.issn1805-9597 (Online)
dc.identifier.urihttp://hdl.handle.net/11025/35139
dc.language.isoenen
dc.publisherZápadočeská univerzita v Plznics
dc.rights© University of West Bohemiaen
dc.rights.accessopenAccessen
dc.subjectoptimalizacecs
dc.subjectkvantizacecs
dc.subjectsignálcs
dc.subjecthlukcs
dc.subjectzpracování digitálních signálůcs
dc.subjectalgoritmy zpracování signálucs
dc.subjectprogramovatelné hradlové polecs
dc.subjectregulátorycs
dc.subject.translatedoptimizationen
dc.subject.translatedquantizationen
dc.subject.translatedsignalen
dc.subject.translatednoiseen
dc.subject.translateddigital signal processingen
dc.subject.translatedsignal processing algorithmsen
dc.subject.translatedfield programmable gate arraysen
dc.subject.translatedregulatorsen
dc.titleController fixed-point optimization with genetic algorithmsen
dc.typekonferenční příspěvekcs
dc.typeconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen

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